Various forms of frequency-based FPGA Design and Implementation

Crossover is the basic design of digital system circuit, according to different design of Xu Yao, we will encounter even frequency, odd-frequency, frequency and half-integer points, Youshiyaoqiu such duty, sometimes requires Fei and other Zhankong Bi . In the same design sometimes requires various forms of frequency. Usually cascaded counter or counters to create various forms of frequency and even the odd non-duty-cycle frequency, etc., to achieve relatively simple. But on the other semi-integer frequency and duty cycle of odd frequency is more difficult to achieve. In this paper, VHDL hardware description language, through the Quartus Ⅱ 3.0 development platform, using Altera's FPGA, designed a way to meet the demands of the more common divider.

1, circuit design

Half-integer divider using FPGA implementation, you can use the following method: Design of a model N of the counter, and then design a pulse less circuit, each net of a pulse to two pulses can achieve frequency division factor of N-0.5 sub-frequency device. Deducted from the pulse circuit XOR gate and a 2-divider constituted. Half-integer divider of the design based on the principle of XOR gate plus an enable control signal, through the XOR gate and the counter counts the value of the control of the state, to achieve the same frequency forms a complete circuit, as shown 1 shows.

Various forms of frequency-based FPGA Design and Implementation

Second, VHDL language to achieve

Can be achieved is through the design of a frequency of 8.5 points, and so the duty cycle of 17 minutes frequency, 2,4,8,16,32 frequency and duty cycle of 1:8 and 4:5 frequency division and other 9 form of frequency divider, to introduce the common divider of the FPGA.

Figure 1 shows the circuit schematic can see, with a divider enabled by the end of the XOR gates, counters and a two-mode N divider composed of D flip-flop to use this design to the completion of two functions of frequency, Implementation is: will trigger the Q output fed back against the input D, a count of the counter output as the D flip-flop clock input. Each functional module VHDL language is as follows.

1. Implementation of N counter module
Counter used in the general design, we can call the lpm library counter module can also be used to design a model VHDL language own N counter. This design uses VHDL language to design a maximum modulus value of 16 counters. Input port: enable signal en, reset signals and clock signal clr clk; output port: qa, qb, qc, qd. Brief description of the VHDL language.

2. With enable control of the realization of XOR gates

Input is: xor_en: XOR enabled, a and b: different or input; output is: c: XOR output. When xor_en is high, c output a and b of different or value. When xor_en is low when, c output signal b. The VHDL language slightly.

3.2 frequency (trigger) the realization of

Inputs are: the clock signal clk, input signal d; output is: q: output signal a, q1: output signal a counter. The VHDL language slightly.

4. Divider implementation

This design uses a hierarchical design approach, Design and Implementation of the first divider circuit composed of circuit elements each, then the method of component cases, call the components, to achieve the divider. The VHDL language slightly.

3, simulation results and test hardware

The purpose of this design is the versatility and simplicity, as long as the program is modified, the frequency can be realized in various forms.

1. Frequency and so on to achieve 8.5 duty cycle of 17 frequency

As long as the above procedure, called the counter module port qa, qb, qc match for the open state, you can also set xor_en is high. Seen from the report compiled a total of 8 logic cells occupied (logic elements), the simulation waveform shown in Figure 2 to 4.

Various forms of frequency-based FPGA Design and Implementation of plans

Figure 2

Various forms of frequency-based FPGA Design and Implementation

Figure 3

Various forms of frequency-based FPGA Design and Implementation

Figure 4

The figure qxiao and clk waveform can be seen every 8.5 clock cycles, qxiao signal produces a rising edge to achieve the frequency sub-band coefficient is 8.5, while qzheng side by 17 points and so the duty cycle frequency . Set clk to 170MHz, the qxiao output is 20MHz, qzheng output is 10MHz.

2. To achieve a duty cycle of 1:8 and 4:5 frequency division 9

As long as the procedure xor_en set low duty cycle can be output in qxiao 9 points for the 1:8 frequency signal; in qzheng2 output duty cycle of 4:5 frequency signal 9. Similarly, only 8 logic elements (logic elements). Simulation waveforms are as follows.

3. Realization of 2,4,8,16 and 32 minutes duty cycle frequency

As long as the proceedings xor_en set to low, while the maximum count of the counter module can be set to 16. Simulation waveforms are as follows.

Thus, the counter counts the slightest change in state value of XOR gates, gating control, you can achieve these various forms of frequency. The design of Altera Corporation in the form EP1K50QC208-3 test platform tested and good performance.

Conclusion

We are in the design of analog radar pulse signals and development of spread spectrum with the FPGA chip is used when the frequency of the various forms of scoring. This paper presents a development for FPGA, the required frequency of the realization of a variety of methods, if the frequency required in the form of design more, you can directly use the design altered slightly by the program to meet the requirements of their own design . If the design requires less frequency form, you can use some of the design process to save resources.