The CAN bus based on 82 527 smart sensor node design

Abstract: This paper introduces a kind of independence of 8051 and 82527 CAN bus controller core component of the CAN bus design method of smart sensor nodes and gives the hardware schematics and initialization procedures.

Introduction

CAN (Controller Area Network, Controller Area Network) from the industrial field bus, a German Bosch company of the 20th century the early 80s as a solution in many modern vehicle control and test instruments developed for data exchange between a communication protocol. November 1993, ISO issued a formal high-speed local area network communication control (CAN) international standard (ISO11898). CAN bus system in the field of data collection completed by the sensor, at present, the sensor with CAN bus interface type is not much more expensive price. This article describes a 8051 and 82,527 by the independent CAN bus controller core components of the intelligent node circuit, formed the basis of ordinary sensors can receive 8 analog inputs and smart sensor nodes.

The CAN bus based on 82 527 smart sensor node design

1 Introduction independent CAN bus controller 82527

Intel 82527 is produced by independent CAN bus controller, through the parallel bus with Intel and Motrorola controller interface; support the CAN 2.0B standard protocols, with the receive and transmit functions and can complete the message filtering. 82 527 manufacturing process by CHMOS 5V, 44-pin PLCC package, use the temperature of -44 ~ 125 ℃, the pin arrangement and definitions see [1].

(1) 82 527 of the clock signal

82 527 run by the two kinds of clock control: the system clock SCLK and register clock MCLK. Obtained from the external crystal SCLK, MCLK SCLK frequency was on. CAN bus bit timing according to the frequency of SCLK, while the MCLK to provide the clock for the register operation. SCLK frequency can be equal to an external crystal XTAL, it can be the frequency 1 / 2; MCLK or SCLK frequency can be equal to the frequency of 1 / 2. After system reset the default setting is SCLK = XTAL / 2, MCLK = SCLK / 2.

(2) 82 527 working mode

82527 5 working modes: Intel mode 8-bit time-multiplexed mode; Intel 16-bit time division multiplexing manner mode; serial interface mode; non-Intel 8-bit time division multiplexing manner mode; 8-bit non-time division multiplexing mode. In this paper, Intel 8-bit time division multiplexing manner mode, this time 82 527, 30 and 44 feet grounded.

(3) 82527 register structure [2]

82527 register address is 00 ~ FFH. The following registers which are introduced as needed.

① Control Register (00H):

76,543,210
0 CCE 0 0 EIE SIE IE INIT

CCE - change the configuration allows bit, high efficient. Effective when the bit configuration registers allow the CPU 1FH, 2FH, 3FH, 4FH, 9FH, AFH write.

EIE - Error interrupt allows spaces, high efficient. The position generally set to 1, when the number of bus error exception generated interrupt CPU.

SIE - Status change interrupt allows spaces, high efficient. The position normally set to 0.

IE - Interrupt Enable bit, high efficient.

INIT - initialize software allows spaces, high efficient. The bit valid, CAN stop sending and receiving messages, TX0 and TX1 recessive level 1. Hardware reset and the bus turned off the bit is set.

② CPU Interface register (02H):

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RSTST DSC DMC PWD SLEEP MUX 0 CEN

RSTST - hardware reset status bits. The bit is written by the 82 527 for 1 hardware reset activation, are not allowed on the 82,527 visits; to 0 to allow access to the 82,527.

DSC - SCLK frequency spaces. The bit is 1, SCLK = XTAL / 2; to 0, SCLK = XTAL.

DMC - MCLK frequency spaces. The bit is 1, MCLK = SCLK / 2; to 0, MCLK = SCLK.

PWD - Power-down mode enable bit, high efficient.

SLEEP - Sleep mode enable bit, high efficient.

MUX - low-speed physical layer multiplexing flag. The bit is 1, ISO low speed physical layer activation, PIN24 = VCC / 2, PIN11 = INT # (# that take anti-); the bit is 0, PIN24 = INT #, PIN11 = P2.6.

CEN - clock output enable bit, high efficient.

③ Standard Global Mask Register (06 ~ 07H). The register has a standard identifier for the packet, or packets XTD set 0 register. The approach is called message receiver filtering. When a is 1, the corresponding packet identifier bits must match; to 0, do not match.

④ extended global mask registers (08 ~ 0BH). The register is used to extend the message format, or set a packet XTD register, its role and ③ the same.

76,543,210
0 COBY POL 0 DCT1 0 DCR1 DCR0

⑤ bus configuration register (2FH):

COBY - bypass input comparator flag, active HIGH.

POL - Polarity flag. 1, if the bypass input comparator, RX0 dominant input logic 1, logic 0 is hidden; to 0, and vice versa.

DCT1 - TX1 output cut off control bit. To 1, TX1 output is not driven, the model case for a bus, two differential wires short-circuit; to 0, TX1 output is driven.

DCR1 - RX1 input cut off control bit. To 1, RX1 comparator inverting input terminal is disconnected, connected to VCC / 2; to 0, RX1 comparator connected to the inverting input terminal.

DCR0 - RX0 input cut off control bit. Role and DCR1 same time RX0 comparator connected to the inverting terminal.

76,543,210
SJW BRP

⑥ Bit Timing Register 0 (3FH);

SJW - Synchronization Jump Width bits field, programmed value of 1 to 3.

BRP - baud rate frequency bit field, programmed value of 0 to 63.

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SPL TSEG2 TSEG1

⑦ Bit Timing Register 1 (4FH):

SPL - sampling mode flag. 1 for each sampled three times; 0 1 for each sample.

TSEG1 - time a field value of 2 to 15 programming.

TSEG1 - time two games, programming value of 1 to 7.

Baud rate = XTAL / [(DSC 1) * (BRP 1) * (3 TSEG1 TSEG2)]

⑧ message register (1 of each register byte address as the base address BASE).

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BASE 0 MSGVAL TXIE RXIE INTPND
BASE 1 RMTPND TXRQST MSGLST / CPUUPD NEWDAT

◇ control register 0,1 (BASE 0, BASET 1)

MSGVAL - Message register valid flag, active HIGH. 10 set, 01 reset.

TXIE - Send interrupt to allow flag, active HIGH. 10 set, 01 reset.

RXIE - Receive interrupt flag to allow, high efficient, 10 set, 01 reset.

INTPND - interrupt flag bit applications, active HIGH. 10 set, 01 reset.

RMTPND - remote frame for flag, active HIGH. 10 set, 01 reset.

TXRQST - request to send flag, active HIGH. 10 set, 01 reset.

MSGLST - packet loss flag is only used to receive message registers. 10 indicates that no newspaper article covered by the new message, 01 that are not covered.

CPUUPD - CPU update flag is only used to send messages register. 10 packets being sent 01 messages can be sent.

NEWDAT - new data flag. 10 that new data is written to the register, 01, said no new data is written.

◇ arbitration register 0,1,2,3 (BASE 2-BASE 5)

Stored message identifier.

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DLC DIR XTD reserved

◇ message configuration register (BASE 6)

DLC - Data length code, the programming value of 0 ~ 8.

DIR - Direction flag. 1 sent, 0 received.

XTD - standard / extended identifier flag. An extension identifier, 0 standard identifier.

◇ Data register (BASE 7-BASE 14)

82,527 store packets, the 8 data bytes are written, not used bytes of data is random.

2 hardware design

Intelligent node circuit shown in Figure 1 (shown in 6264 spent).

In hardware design, complete by the ADC0809 8-channel analog set conversion, and the 8051 inquiry by way of exchange of information, address BFF8 ~ BFFFH, its clock frequency obtained by the ALE 2; 82,527 to complete the exchange of information with the CAN bus. The design, bypass the input comparators, and the 8051 information exchange with interrupt, address 7F00 ~ 7FFFH, can use 82,527 of the P1 and P2 port on the switch port traffic acquisition or control of the relay. 82C250 provides 82 527 and the physical interface between the bus and improve capacity to receive and send. Program memory can be expanded as needed.

3 Software Design

The design software is written in MCS-51 assembly, the block diagram shown in Figure 2.

The CAN bus based on 82 527 smart sensor node design

82527 initialization procedure is as follows:

INT: MOV DPTR, # 0FF02H
MOV A, # 00H
MOVX @ DPTR, A; SCLK = XTAL
; MCLK = SCLK, CLKOUT valid
MOV DPTR, # 0FF00H
MOV A, # 41H
MOVX @ DPTR, A; Set CCE, INIT
MOV DPTR, # 0FF2FH
MOV A, # 48H
MOVX @ DPTR, A; bypass input comparator to set a hidden, 0 is dominant, RX1 invalid
MOV DPTR, # 0FF3FH;
MOV A, # 43H;
MOVX @ DPTR, A; SJW = 2, BRP = 3
MOV DPTR, # 0FF4FH
MOV A, # 0EAH
MOVX @ DPTR, A; SPL = 1, TSEG1 = 7, TSEG2 = 6 then the baud rate is 100Kbps
MOV DPTR, # 0FF00H;
MOV A, # 01H
MOVX @ DPTR, A; prohibit access to the configuration register
MOV DPTR, # 0FF10H;
MOV A, # 55H;
MOVX @ DPTR, A;
INC DPTR;
MOVX @ DPTR, A;
*
*
*
MOV DPTR, # 0FFF0H;
MOV A, # 55H;
MOVX @ DPTR, A
INC DPTR;
MOVX @ DPTR, A; message control bit register initialization
MOV R0, # 06H;
MOV DPTR, # 0FF06H;
MOV A, # 0FFH;
L1: MOVX @ DPTR, A; message identifier need all the match
INC DPTR
DJNZ R0, L1;
MOV DPTR, # 0FF16H;
MOV A, # 8CH; message register 1 can be extended to send 8 bytes packet
MOVX @ DPTR, A;
MOV DPTR, # 0FF26H;
MOV A, # 84H;
MOVX @ DPTR, A; message register 2 can be extended to receive eight-byte packets
MOV DPTR, # 0FF00H;
MOV A, # 00H;
MOVX @ DPTR, A; Initialization end
RET